The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, it relates to a semiconductor integrated circuit device having an MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a high breakdown voltage and that having a low breakdown voltage on the same semiconductor substrate, and a method of manufacturing the same.
The MISFET having a high breakdown voltage is used for a driver of a liquid crystal display, a motor control driver for controlling a high electric current or a non-volatile memory which requires high voltage for programming.
This MISFET having a high breakdown voltage is designed to increase the breakdown voltage in various ways, for example, by thickening a gate insulating film.
In Japanese Patent Application Laid-Open No. Hei 11(1999)-177047, described is a technique of forming the gate insulating film 10 of one of a plurality of electric field effect transistors different in thickness of a gate insulating film with a laminate of a thermal oxide film 8 and a deposited film 9.
In Japanese Patent Application Laid-Open No. 2000-68385 (corresponding to U.S. patent Ser. No. 09/208,019), described is a technique of simultaneously forming a electric field relaxing region NW (FD) of a high breakdown voltage NMOS transistor and a channel stopper NW (CS) in a well region NW of a low breakdown voltage PMOS transistor and in a well HNW region of a high breakdown voltage PMOS transistor.
The present inventors investigated an improvement in drain breakdown voltage by disposing electric field relaxation layers 9,8 in the vicinity of sourcexe2x80xa2drain regions 17,18 of a high breakdown voltage MISFET (Qn2,Qp2) as illustrated in FIG. 40.
In the structure of MISFET as illustrated in FIG. 40, however, owing to thinness of a gate insulating film 5 below a gate electrode FG, the gate insulating film was broken at its end portions, making it impossible to maintain a breakdown voltage. In addition, since the electric field relaxation layers 9,8 were separately disposed at both ends of the sourcexe2x80xa2drain regions 17,18, electric field effect concentration tended to occur on the boundary between the electric field relaxation layer and sourcexe2x80xa2drain regions. As a result, problems such as lowering in drain breakdown voltage or lowering in electrostatic breakdown strength occurred.
In order to relax electric field effect concentration on the boundary between the electric field relaxation layer and sourcexe2x80xa2drain regions, thereby solving one of the above-described problems, a structure, as illustrated in FIG. 41, of covering the sourcexe2x80xa2drain regions 17,18 with the electric field relaxation layers 9,8 was investigated. The problem, that is, lowering in breakdown voltage due to breakage of the gate insulating film 5 at the end portions of the gate electrode has not yet been dissolved solved.
An improvement in breakdown voltage by disposing a field oxide film 4a at the end portions of the gate electrode FG as illustrated in FIG. 42 was investigated, but failed to relax electric field effect concentration on the boundary between the electric field relaxation layers 9,8 and sourcexe2x80xa2drain regions 17,18.
Functions of the members illustrated in FIGS. 40 to 42 are presumed to become apparent later by Embodiments of the present invention so that a detailed description is omitted.
An object of the present invention is to provide a miniaturized structure of high breakdown voltage MISFET and a manufacturing method of the structure.
Another object of the present invention is to provide a high breakdown voltage MISFET structure suppressed in the influence of a parasitic MOS and a manufacturing method of the structure.
A further object of the present invention is to provide a structure of a high breakdown voltage MISFET having a high performance and a manufacturing method of the structure.
The above-described and the other objects, and novel features of the present invention will be apparent from the description herein and accompanying drawings.
Among the aspects of the invention disclosed by the present application, some principal ones will next be described.
In a first aspect of the present invention, there is thus provided a manufacturing method of a semiconductor integrated circuit device, which comprises forming a first insulating film between two adjacent regions of first MISFET forming regions and second MISFET forming regions, forming second and third insulating films on the surface of a semiconductor substrate between the first insulating films, forming a first conductive film over the third insulating film of a second region wherein the second MISFET is to be formed, forming a fourth insulating film in a first region wherein the first MISFET is to be formed after removal of the third and second insulating films over the first region, and forming a second conductive film over the fourth insulating film, wherein the third insulating film remains over the first insulating film of the second region.
In a second aspect of the present invention, there is also provided a method of a semiconductor integrated circuit device which comprises forming a first insulating film between two adjacent regions of first MISFET forming regions and second MISFET forming regions, forming a first semiconductor region and a second semiconductor region in a first region wherein the first MISFET is to be formed and in a second region wherein the second MISFET is to be formed, respectively, forming second and third insulating films in the first and second regions, removing the third and second insulating films from the first region and removing a portion of the second and third insulating films over the second semiconductor region in the second region, thereby forming a first opening portion, forming a first conductive film to be a gate electrode of the second MISFET over the third insulating film in the second region, forming a fourth insulating film in the first region, forming a second conductive film to be a gate electrode of the first MISFET over the fourth insulating film, and introducing an impurity into a surface of the semiconductor substrate in order to form a third semiconductor region having a conductivity type contrary to that of the first semiconductor region on both sides of the gate electrode of the first region and to form a fourth semiconductor region having the same conductivity type as that of the second semiconductor region below the first opening in the second region.
In a third aspect of the present invention, there is also provided a manufacturing method of a semiconductor integrated circuit device, which comprises forming a first insulating film in a first region wherein a first MISFET is to be formed and a second region wherein a second MISFET is to be formed, depositing a first conductive film over the first insulating film in the first and second regions, removing the first insulating film and first conductive film from the first region, forming a second insulating film in the first region over the semiconductor substrate, depositing a second conductive film over the first and second regions, and implanting an impurity downward from a position above the second conductive film into the first and second regions at an energy permitting the impurity to reach the substrate of the first region.
In a fourth aspect of the present invention, there is also provided a semiconductor integrated circuit device comprising a first insulating film lying between two adjacent regions of first MISFET forming regions in a first region wherein a first MISFET is to be formed and second MISFET forming regions in a second region wherein a second MISFET is to be formed, a second insulating film formed in the second region, a third insulating film formed over the first insulating film and second insulating film in the second region, a first conductive film over the third insulating film in the second region, a fourth insulating film formed in the first region, and a second conductive film formed over the fourth insulating film in the first region.
In a fifth aspect of the present invention, the semiconductor integrated circuit device further comprises a second semiconductor region formed in the semiconductor substrate of the second region and having a conductivity type contrary to that of the first semiconductor region formed in the first region, a third insulating film having a first opening over the second semiconductor region in the second region and formed over the first and second insulating films and a fourth semiconductor region of the same conductivity type formed below the first opening and in the second semiconductor region.
In a sixth aspect of the present invention, there is also provided a semiconductor integrated circuit device comprising a first insulating film lying between two adjacent regions of MISFET forming regions in each of a first region wherein a first MISFET is to be formed and a second region wherein a second MISFET is to be formed, a second insulating film formed over the surface of the semiconductor substrate in the second region, a third insulating film formed in the second region, a first conductive film formed over the third insulating film in the second region, a fourth insulating film formed over the surface of the semiconductor substrate in the first region and a second conductive film formed over the fourth insulating film in the first region.